This application claims priority to Korean Patent Application No. 2001-68197 filed on Nov. 2, 2001.
1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to an internal power voltage generating circuit for use in a semiconductor memory device.
2. Description of Related Art
Typically, an internal power voltage generating circuit for use in a semiconductor memory device detects a voltage difference between a reference voltage and an internal power voltage and controls the level of the internal power voltage based on the voltage difference.
FIG. 1 is a circuit diagram illustrating a conventional power voltage generating circuit for use in a semiconductor memory device. The internal power voltage generating circuit comprises a PMOS transistor P3, a capacitor CL, and a current mirror type comparator 10 comprising PMOS transistors P1 and P2, NMOS transistors N1 and N2, and a constant current source Is. A load current IL represents current flowing through a load connected to an internal power voltage generating terminal.
When a reference voltage level VREF is greater than an internal power voltage level VINT, the NMOS transistor N1 is turned on and the current mirror type comparator 10 lowers the voltage of node A. The PMOS P3 transistor is turned on, and the current supplied to the internal power voltage generating terminal VINT is increased, thereby steadily raising the internal power voltage level VINT through the capacitor CL.
Alternately, when the reference voltage level VREF is lower than the internal power voltage level VINT, the NMOS transistor N2 is turned on and the current mirror type comparator 10 raises the voltage of node A. The PMOS transistor P3 is turned off and the current supplied to the internal power voltage generating terminal VINT is decreased, thereby steadily lowering the internal power voltage level VINT through the capacitor CL.
When the level of the load current IL becomes 0, the PMOS transistor P3 has to be turned off to prevent current flowing to the internal power voltage VINT. However, it takes time to turn off the PMOS transistor P3 after the level of the load current IL becomes 0, due to the comparing operation of the current mirror type comparator 10 for raising the gate voltage of the PMOS transistor P3. Thus, current flows through the PMOS transistor P3 during the time between the level of load current IL being 0 and the PMOS transistor P3 being turned off. Accordingly, the level of the internal power voltage is raised and an overshoot of the internal power voltage occurs in the internal power voltage generating circuit of FIG. 1.
FIG. 2 is a circuit diagram illustrating another conventional internal power voltage generating circuit. The internal power voltage generating circuit of FIG. 2 comprises NMOS transistors N3(1) to N3(n) in parallel connected between node B and a ground voltage, in addition to components of the internal power voltage generating circuit of FIG. 1. Referring to FIG. 2, when the voltage of node B is greater than a voltage (nxc3x97Vth), the NMOS transistors N3(1) to N3(n) are turned on and the current flowing through the PMOS transistor P3 streams down to the ground voltage. Here, Vth denotes a threshold voltage of each of the NMOS transistors N3(1) to N3(n).
When the level of the load current IL becomes 0, the NMOS transistors N3(1) to N3(n) are turned on and the current flowing through the PMOS transistor P3 flows to the transistors N3(1) to N3(n), thereby lowering the internal power voltage VINT to a desired voltage level.
FIG. 3 is a graph illustrating a relationship between the internal power voltage and the current flowing to the NMOS transistors N3(1) to N3(n) based on the number of the NMOS transistors of FIG. 2.
For example, when one NMOS transistor is connected between node B and the ground voltage, current begins to flow through the NMOS transistor N3(1) at the internal power voltage of about 0.4 volts. When two NMOS transistors are connected between node B and the ground voltage, current begins to flow through the NMOS transistors N3(1), N3(2) at the internal power voltage of about 0.9 volts. When five NMOS transistors are connected between node B and the ground voltage, current begins to flow through the NMOS transistors N3(1) to N3(5) at the internal power voltage of about 3.5 volts.
That is, the level of the internal power voltage at which current begins to flow from node B to the ground voltage largely depends on the number of the NMOS transistors N3(1) to N3(n). Therefore, it is difficult to accurately set the internal power voltage level when an overshoot occurs.
For example, current begins to flow from node B to the ground voltage at the internal power voltage of about 0.9 volts when two NMOS transistors N3(1) to N3(2) are connected between node B and the ground voltage, whereas current begins to flow from node B to the ground voltage at the internal power voltage of about 1.7 volts when three NMOS transistors N3(1) to N3(2) are connected between node B and the ground voltage. Therefore, it is impossible to set the level of current flowing from node B to the ground voltage when the internal power voltage VINT becomes 1.3 volts.
It is an object of the present invention to provide an internal power voltage generating circuit capable of accurately adjusting a level of an internal power voltage in response to an overshoot of the internal power voltage.
According to an aspect of the present invention, an internal power voltage generating circuit comprises an internal power voltage generator for generating an internal power voltage to an internal power voltage generating terminal, first and second resistor devices, serially connected between the internal power voltage generating terminal and a ground voltage, for distributing the internal power voltage and for generating a distributed voltage to a distributed voltage generating node, and a current discharging device, connected between the internal power voltage generating terminal and the ground voltage, for discharging current from the internal power voltage generating terminal to the ground voltage in response to the distributed voltage.
According to another aspect of the present invention, an internal power voltage generating circuit comprises an internal power voltage generator for generating an internal power voltage to an internal power voltage generating terminal, a variable resistor device connected between the internal power voltage generating terminal and a ground voltage, for distributing the internal power voltage and for generating a distributed voltage to a distributed voltage generating node, and a current discharging device, connected between the internal power voltage generating terminal and the ground voltage, for discharging current from the internal power voltage generating terminal to the ground voltage in response to the distributed voltage.
According to another aspect of the present invention, an internal power voltage generating circuit comprises an internal power voltage generating means for generating an internal power voltage to an internal power voltage generating terminal, a first resistor means connected between the internal power voltage generating terminal and a distributed voltage generating node in which the internal power voltage is distributed, a second resistor means connected between the distributed voltage generating node and a ground voltage, the second resistor means comprising a variable resistance value, and a current discharging means, connected between the internal power voltage generating terminal and the ground voltage, for discharging current from the internal power voltage generating terminal to the ground voltage in response to the distributed voltage.
According to further aspect of the present invention, an internal power voltage generating circuit comprises an internal power voltage generating circuit for generating an internal power voltage to an internal power voltage generating terminal, a first resistor device connected between the internal power voltage generating terminal and a distributed voltage generating node for distributing the internal power voltage, a second resistor device connected between the distributed voltage generating node and a ground voltage, and a current discharging device connected between the internal power voltage generating terminal and the ground voltage and for discharging current from the internal power voltage generating terminal to the ground voltage in response to the distributed voltage.
These and other aspects, factors, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in conjunction with the accompanying figures.